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| kl26p64m48sf5 kl26 sub-family data sheet supports the following: mkl26z32vfm4, mkl26z64vfm4, mkl26z128vfm4, mkl26z32vft4, mkl26z64vft4, mkl26z128vft4, mkl26z32vlh4, mkl26z64vlh4, MKL26Z128VLH4 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 105c ? performance C up to 48 mhz arm? cortex-m0+ core ? memories and memory interfaces C 128 kb program flash memory C 16 kb ram ? clocks C 32 khz to 40 khz or 3 mhz to 32 mhz crystal oscillator C multi-purpose clock source ? system peripherals C nine low-power modes to provide power optimization based on application requirements C 4-channel dma controller, supporting up to 63 request sources C cop software watchdog C low-leakage wakeup unit C swd interface and micro trace buffer C bit manipulation engine (bme) ? security and integrity modules C 80-bit unique identification (id) number per chip ? human-machine interface C low-power hardware touch sensor interface (tsi) C general-purpose input/output ? analog modules C 16-bit sar adc C 12-bit dac C analog comparator (cmp) containing a 6-bit dac and programmable reference input ? timers C six channel timer/pwm (tpm) C two 2-channel timer/pwm (tpm) C periodic interrupt timers C 16-bit low-power timer (lptmr) C real-time clock ? communication interfaces C usb full-/low-speed on-the-go controller with on- chip transceiver and 5 v to 3.3 v regulator C two 16-bit spi modules C two i2c modules C i2s (sai) module C one low power uart module C two uart modules freescale semiconductor document number: kl26p64m48sf5 data sheet: technical data rev. 2, 10/2013 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2013 freescale semiconductor, inc.
table of contents 1 ordering parts ........................................................................... 3 1.1 determining valid orderable parts...................................... 3 2 part identification ...................................................................... 3 2.1 description......................................................................... 3 2.2 format ............................................................................... 3 2.3 fields ................................................................................. 3 2.4 example ............................................................................ 4 3 terminology and guidelines ...................................................... 4 3.1 definition: operating requirement...................................... 4 3.2 definition: operating behavior ........................................... 4 3.3 definition: attribute ............................................................ 5 3.4 definition: rating ............................................................... 5 3.5 result of exceeding a rating .............................................. 6 3.6 relationship between ratings and operating requirements...................................................................... 6 3.7 guidelines for ratings and operating requirements............ 6 3.8 definition: typical value..................................................... 7 3.9 typical value conditions .................................................... 8 4 ratings ...................................................................................... 8 4.1 thermal handling ratings ................................................... 8 4.2 moisture handling ratings .................................................. 8 4.3 esd handling ratings ......................................................... 8 4.4 voltage and current operating ratings ............................... 9 5 general ..................................................................................... 9 5.1 ac electrical characteristics .............................................. 9 5.2 nonswitching electrical specifications ............................... 10 5.2.1 voltage and current operating requirements ......... 10 5.2.2 lvd and por operating requirements ................. 11 5.2.3 voltage and current operating behaviors .............. 11 5.2.4 power mode transition operating behaviors .......... 12 5.2.5 power consumption operating behaviors .............. 13 5.2.6 emc radiated emissions operating behaviors....... 19 5.2.7 designing with radiated emissions in mind ........... 20 5.2.8 capacitance attributes .......................................... 20 5.3 switching specifications..................................................... 20 5.3.1 device clock specifications ................................... 20 5.3.2 general switching specifications ........................... 21 5.4 thermal specifications ....................................................... 21 5.4.1 thermal operating requirements ........................... 21 5.4.2 thermal attributes ................................................. 21 6 peripheral operating requirements and behaviors .................... 22 6.1 core modules .................................................................... 22 6.1.1 swd electricals .................................................... 22 6.2 system modules ................................................................ 23 6.3 clock modules ................................................................... 24 6.3.1 mcg specifications ............................................... 24 6.3.2 oscillator electrical specifications ......................... 25 6.4 memories and memory interfaces ..................................... 28 6.4.1 flash electrical specifications................................ 28 6.5 security and integrity modules .......................................... 29 6.6 analog ............................................................................... 29 6.6.1 adc electrical specifications ................................. 29 6.6.2 cmp and 6-bit dac electrical specifications ......... 34 6.6.3 12-bit dac electrical characteristics ..................... 36 6.7 timers................................................................................ 39 6.8 communication interfaces ................................................. 39 6.8.1 usb electrical specifications ................................. 39 6.8.2 usb vreg electrical specifications ...................... 39 6.8.3 spi switching specifications .................................. 40 6.8.4 inter-integrated circuit interface (i2c) timing ........ 44 6.8.5 uart .................................................................... 45 6.8.6 i2s/sai switching specifications............................ 46 6.9 human-machine interfaces (hmi)...................................... 50 6.9.1 tsi electrical specifications ................................... 50 7 dimensions ............................................................................... 50 7.1 obtaining package dimensions ......................................... 50 8 pinout ........................................................................................ 51 8.1 kl26 signal multiplexing and pin assignments ................ 51 8.2 kl26 pinouts ..................................................................... 53 kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 2 freescale semiconductor, inc. 1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to freescale.com aerformaarumbersearcfore follogeceumbersa arefcao . escro arumbersforecaefelsaefesecfcar.oucausee aluesofesefelsoeermeesecfcarouaerecee. . orma arumbersforseceaeefollogforma . els sablelsseossblealuesforeacfelearumberoallcombaos areal el escro alues ualfcaosaus ullualfegeeralmareflo reualfcao esfaml earbue ore rogramflasmemorse lcoreso laa esoaferma table continues on the next page... rdering parts l2 sub-family data sheet data sheet, rev. 2, 10/201. freescale semiconductor, inc. field description values t temperature range (c) v = ?40 to 105 pp package identifier fm = 32 qfn (5 mm x 5 mm) ft = 48 qfn (7 mm x 7 mm) lh = 64 lqfp (10 mm x 10 mm) cc maximum cpu frequency (mhz) 4 = 48 mhz n packaging type r = tape and reel 2.4 example this is an example part number: mkl26z128vfm4 3 terminology and guidelines 3.1 definition: operating requirement an operating requirement is a speciied value or range o values or a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useul lie o the chip ample his is an eample o an operating requirement ymbol escription in a nit core supply voltage einition operating behavior n operating behavior is a speciied value or range o values or a technical characteristic that are guaranteed during operation i you meet the operating requirements and any other speciied conditions erminology and guidelines ubamily ata heet ata heet ev reescale emiconductor nc 3.2.1 example this is an example of an operating behavior: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 3.3 definition: attribute an attribute is a speciied value or range o values or a technical characteristic that are guaranteed regardless o hether you meet the operating requirements ample his is an eample o an attribute ymbol escription in a nit nput capacitance digital pins p einition ating rating is a minimum or maimum value o a technical characteristic that i eceeded may cause permanent chip ailure operating ratings apply during operation o the chip handling ratings apply hen the chip is not poered ample his is an eample o an operating rating ymbol escription in a nit core supply voltage erminology and guidelines ubamily ata heet ata heet ev reescale emiconductor nc 3.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 3.6 relationship between ratings and operating requirements ? 3.8 definition: typical value a typical value is a speciied value or a technical characteristic that ies ithin the range o values speciied by the operating behavior iven the typical manuacturing process is representative o that characteristic during operation hen you meet the typicalvalue conditions or other speciied conditions ypical values are provided as design guidelines and are neither tested nor guaranteed ample his is an eample o an operating behavior that includes a typical value ymbol escription in yp a nit igital o ea pulluppulldon current ample his is an eample o a chart that shos typical values or various voltage and temperature conditions o erminology and guidelines ubamily ata heet ata heet ev reescale emiconductor nc 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): table 1. typical value conditions symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 4 ratings 4.1 thermal handling ratings table 2. thermal handling ratings symbol description min. max. unit notes t stg storage temperature ?55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . .2 moisture handling ratings table . moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . ratings l2 sub-family data sheet data sheet, rev. 2, 10/201. freescale semiconductor, inc. 4.3 esd handling ratings table 4. esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model ?2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model ?500 +500 v 2 i lat latch-up current at ambient temperature of 105 c ?100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . . determined according to jedec standard jesd, ic latch-up test . . oltage and current operating ratings table 5. oltage and current operating ratings symbol description min. max. unit dd digital supply voltage 0. . i dd digital supply current 120 ma i i pin input voltage 0. dd 0. i d instantaneous maximum current single pin limit (applies to all port pins) 25 25 ma dda analog supply voltage dd 0. dd 0. usbdp usbdp input voltage 0. . usbdm usbdm input voltage 0. . regin usb regulator input 0. .0 5 general 5.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50 to the 50 point, and rise and fall times are measured at the 20 and 0 points, as shown in the following figure. general l2 sub-family data sheet data sheet, rev. 2, 10/201. freescale semiconductor, inc. figure 1. input signal measurement reference all digital i/o switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. ? c l =30 pf loads ? slew rate disabled ? normal drive strength 5.2 nonswitching electrical specifications 5.2.1 voltage and current operating requirements table 6. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd ? v dda v dd -to-v dda differential voltage ?0.1 0.1 v v ss ? v ssa v ss -to-v ssa differential voltage ?0.1 0.1 v v ih input high voltage 2.7 v ? v dd ? 3.6 v 1.7 v ? v dd ? 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage 2.7 v ? v dd ? 3.6 v 1.7 v ? v dd ? 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icio io pin negative dc injection current single pin v in < v ss -0.3v -3 ma 1 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents of 16 contiguous pins negative current injection -25 ma table continues on the next page... general l2 sub-family data sheet data sheet, rev. 2, 10/201. 10 freescale semiconductor, inc. table 6. voltage and current operating requirements (continued) symbol description min. max. unit notes v odpu open drain pullup voltage level v dd v dd v 2 v ram v dd voltage required to retain ram 1.2 v 1. all i/o pins are internally clamped to v ss through a esd protection diode. there is no diode connection to v dd . if v in greater than v io_min (= v ss -0.3 v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r = (v io_min - v in )/|i icio |. 2. open drain outputs must be pulled to v dd . 5.2.2 lvd and por operating requirements table 7. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling v dd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv = 01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range level 1 falling (lvwv = 00) level 2 falling (lvwv = 01) level 3 falling (lvwv = 10) level 4 falling (lvwv = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range level 1 falling (lvwv = 00) level 2 falling (lvwv = 01) level 3 falling (lvwv = 10) level 4 falling (lvwv = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 40 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 ?s 1. rising thresholds are falling threshold + hysteresis voltage general kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 11 5.2.3 voltage and current operating behaviors table 8. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage normal drive pad (except reset_b) 2.7 v ? v dd ? 3.6 v, i oh = -5 ma 1.71 v ? v dd ? 2.7 v, i oh = -2.5 ma v dd ? 0.5 v dd ? 0.5 v v 1 , 2 v oh output high voltage high drive pad (except reset_b) 2.7 v ? v dd ? 3.6 v, i oh = -20 ma 1.71 v ? v dd ? 2.7 v, i oh = -10 ma v dd ? 0.5 v dd ? 0.5 v v 1 , 2 i oht output high current total for all ports 100 ma v ol output low voltage normal drive pad 2.7 v ? v dd ? 3.6 v, i ol = 5 ma 1.71 v ? v dd ? 2.7 v, i ol = 2.5 ma 0.5 0.5 v v 1 v ol output low voltage high drive pad 2.7 v ? v dd ? 3.6 v, i ol = 20 ma 1.71 v ? v dd ? 2.7 v, i ol = 10 ma 0.5 0.5 v v 1 i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range 1 ?a 3 i in input leakage current (per pin) at 25 c 0.025 ?a 3 i in input leakage current (total all pins) for full temperature range 65 ?a 3 i oz hi-z (off-state) leakage current (per pin) 1 ?a r pu internal pullup resistors 20 50 k? 4 1. the reset pin only contains an active pull down device when configured as the reset signal or as a gpio. when configured as a gpio output, it acts as a pseudo open drain output. 2. ptb0, ptb1, ptd6, and ptd7 i/o have both high drive and normal drive capability selected by the associated ptx_pcrn[dse] control bit. all other gpios are normal drive only. 3. measured at v dd = 3.6 v 4. measured at v dd supply voltage = v dd min and vinput = v ss 5.2.4 power mode transition operating behaviors all specifications except t por and vllsx por and vllsx table continues on the next page... general l2 sub-family data sheet data sheet, rev. 2, 10/201. freescale semiconductor, inc. 1 table 10. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_run run mode current - 48 mhz core / 24 mhz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash at 3.0 v at 25 c at 70 c at 125 c 6.0 6.2 6.3 6.5 6.8 7.1 ma ma ma 3 , 4 i dd_wait wait mode current - core disabled / 48 mhz system / 24 mhz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 v 2.7 5.7 ma 3 i dd_wait wait mode current - core disabled / 24 mhz system / 24 mhz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 v 2.1 5.5 ma 3 i dd_pstop2 stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 mhz bus at 3.0 v 2.2 4.1 ma 3 i dd_vlprco _cm very-low-power run mode current in compute operation - 4 mhz core / 0.8 mhz flash / bus clock disabled, lptmr running with 4 mhz internal reference clock, coremark benchmark code executing from flash at 3.0 v 732 ?a 5 i dd_vlprco very-low-power run mode current in compute operation - 4 mhz core / 0.8 mhz flash / bus clock disabled, code of while(1) loop executing from flash at 3.0 v 161 367 ?a 6 i dd_vlpr very-low-power run mode current - 4 mhz core / 0.8 mhz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash at 3.0 v 185 372 ?a 6 i dd_vlpr very-low-power run mode current - 4 mhz core / 0.8 mhz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash at 3.0 v 256 420 ?a 4 , 6 i dd_vlpw very-low-power wait mode current - core disabled / 4 mhz system / 0.8 mhz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 v 110 355 ?a 6 table continues on the next page... general l2 sub-family data sheet data sheet, rev. 2, 10/201. 1 freescale semiconductor, inc. table 10. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_stop stop mode current at 3.0 v at 25 c at 50 c at 70 c at 85 c at 105 c 301 311 342 382 481 428 722 758 809 929 ?a i dd_vlps very-low-power stop mode current at 3.0 v at 25 c at 50 c at 70 c at 85 c at 105 c 2.3 5.2 10.5 19.3 42.3 8.4 18.3 26.1 58.5 105.1 ?a i dd_lls low-leakage stop mode current at 3.0 v at 25 c at 50 c at 70 c at 85 c at 105 c 1.7 3.2 5.8 11.6 26.8 3.3 34.9 38.5 43.8 61.7 ?a i dd_vlls3 very-low-leakage stop mode 3 current at 3.0 v at 25 c at 50 c at 70 c at 85 c at 105 c 1.3 2.3 4.7 8.5 19.5 3.0 17.6 19.5 24.1 35.3 ?a i dd_vlls1 very-low-leakage stop mode 1 current at 3.0v at 25c at 50c at 70c at 85c at 105c 0.7 1.2 2.2 4.8 12.4 1.3 11.7 12.6 15.3 22.6 ?a i dd_vlls0 very-low-leakage stop mode 0 current (smc_stopctrl[porpo] = 0) at 3.0 v at 25 c at 50 c at 70 c at 85 c at 105 c 310 778 1928 3906 10097 844 3861 13055 15457 23116 na table continues on the next page... general l2 sub-family data sheet data sheet, rev. 2, 10/201. freescale semiconductor, inc. 15 table 10. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vlls0 very-low-leakage stop mode 0 current (smc_stopctrl[porpo] = 1) at 3.0 v at 25 c at 50 c at 70 c at 85 c at 105 c 139 600 1674 3554 9580 747 3418 11143 13683 20463 na 7 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module?s specification for its supply current. 2. mcg configured for pee mode. coremark benchmark compiled using iar 6.40 with optimization level high, optimized for balanced. 3. mcg configured for fei mode. 4. incremental current consumption from peripheral activity is not included. 5. mcg configured for blpi mode. coremark benchmark compiled using iar 6.40 with optimization level high, optimized for balanced. 6. mcg configured for blpi mode. 7. no brownout table 11. low power mode peripheral adders typical value symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 56 a i irefsten32khz 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 52 a i erefsten4mhz external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 250 262 266 268 272 274 ua i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. vlls1 vlls3 lls vlps stop 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 na i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a table continues on the next page... general l2 sub-family data sheet data sheet, rev. 2, 10/201. 1 freescale semiconductor, inc. table 11. low power mode peripheral adders typical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 i rtc rtc peripheral adder measured by placing the device in vlls1 mode with external 32 khz crystal enabled by means of the rtc_cr[osce] bit and the rtc alarm set for 1 minute. includes erclk32k (32 khz external crystal) power consumption. 432 357 388 475 532 810 na i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 259 66 271 66 275 66 277 66 281 66 283 a i tpm tpm peripheral adder measured by placing the device in stop or vlps mode with selected clock source configured for output compare generating 100 hz clock signal. no load is placed on the i/o generating the clock signal. includes selected clock source and i/o switching currents. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 86 275 86 288 86 290 86 295 86 300 86 306 a i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 45 a i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low-power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 a 5.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe for run mode, and blpe for vlpr mode ? usb regulator disabled ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfa general kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 17 figure 2. run mode supply current vs. core frequency general kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 18 freescale semiconductor, inc. figure 3. vlpr mode current vs. core frequency 5.2.6 emc radiated emissions operating behaviors table 12. emc radiated emissions operating behaviors symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15?50 16 db?v 1 , 2 v re2 radiated emissions voltage, band 2 50?150 18 db?v v re3 radiated emissions voltage, band 3 150?500 11 db?v v re4 radiated emissions voltage, band 4 500?1000 13 db?v v re_iec iec level 0.15?1000 m 2 , 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 1-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported general l2 sub-family data sheet data sheet, rev. 2, 10/201. freescale semiconductor, inc. 1 emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. v dd = 3.3 v, t a = 25 c, f osc = 8 mhz (crystal), f sys = 48 mhz, f bus = 24 mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method 5.2. designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com . 2. perform a keyword search for emc design. 5.2. capacitance attributes table 1. capacitance attributes symbol description min. max. unit c in input capacitance pf 5. switching specifications 5..1 device clock specifications table 1. device clock specifications symbol description min. max. unit normal run mode f ss system and core clock mhz f bus bus clock 2 mhz f flash flash clock 2 mhz f ssusb system and core clock when full speed usb in operation 20 mhz f lptmr lptmr clock 2 mhz lpr and lps modes 1 f ss system and core clock mhz f bus bus clock 1 mhz f flash flash clock 1 mhz f lptmr lptmr clock 2 2 mhz f ercl external reference clock 1 mhz f lptmrercl lptmr external reference clock 1 mhz table continues on the next page... general l2 sub-family data sheet data sheet, rev. 2, 10/201. 20 freescale semiconductor, inc. table 14. device clock specifications (continued) symbol description min. max. unit f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 16 mhz f tpm tpm asynchronous clock 8 mhz f uart0 uart0 asynchronous clock 8 mhz 1. the frequency limitations in vlpr and vlps modes here override any frequency specification listed in the timing specification for any other module. these same frequency limits apply to vlps, whether vlps was entered from run or from vlpr. 2. the lptmr can be clocked at this speed in vlpr or vlps only when the source is an external pin. 5.3.2 general switching specifications these general-purpose specifications apply to all signals configured for gpio and uart signals. table 15. general switching specifications description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 external reset and nmi pin interrupt pulse width asynchronous path 100 ns 2 gpio pin interrupt pulse width asynchronous path 16 ns 2 port rise and fall time 36 ns 3 1. the greater synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. 3. 75 pf load 5.4 thermal specifications 5.4.1 thermal operating requirements table 16. thermal operating requirements symbol description min. max. unit t j die junction temperature ?40 125 c t a ambient temperature ?40 105 c general kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 21 5.4.2 thermal attributes table 17. thermal attributes board type symbol description 64 lqfp 48 qfn 32 qfn unit notes single-layer (1s) r integrated circuits thermal test method environmental conditions natural convection (still air) , or eia/jedec standard jesd51-, integrated circuit thermal test method environmental conditionsforced convection (moving air) . 2. determined according to jedec standard jesd51-, integrated circuit thermal test method environmental conditions junction-to-board . . determined according to method 1012.1 of mil-std , test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. . determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditions natural convection (still air) . peripheral operating reuirements and behaviors .1 core modules .1.1 swd electricals table 1. swd full voltage range electricals symbol description min. max. unit perating voltage 1.1 . j1 swdcl freuency of operation serial wire debug 0 25 mhz j2 swdcl cycle period 1/j1 ns table continues on the next page... peripheral operating reuirements and behaviors l2 sub-family data sheet data sheet, rev. 2, 10/201. 22 freescale semiconductor, inc. table 18. swd full voltage range electricals (continued) symbol description min. max. unit j3 swd_clk clock pulse width serial wire debug 20 ns j4 swd_clk rise and fall times 3 ns j9 swd_dio input data setup time to swd_clk rise 10 ns j10 swd_dio input data hold time after swd_clk rise 0 ns j11 swd_clk high to swd_dio data valid 32 ns j12 swd_clk high to swd_dio high-z 5 ns j2 j3 j3 j4 j4 swd_clk (input) figure 4. serial wire clock input timing j11 j12 j11 j9 j10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 5. serial wire data timing peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 23 6.2 system modules there are no specifications necessary for the device?s system modules. 6.3 clock modules 6.3.1 mcg specifications table 19. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal v dd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz table continues on the next page... peripheral operating reuirements and behaviors l2 sub-family data sheet data sheet, rev. 2, 10/201. 2 freescale semiconductor, inc. table 19. mcg specifications (continued) symbol description min. typ. max. unit notes j cyc_fll fll period jitter f vco = 48 mhz 180 ps 7 t fll_acquire fll target frequency acquisition time 1 ms 8 pll f vco vco operating frequency 48.0 100 mhz i pll pll operating current pll at 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) 1060 a 9 i pll pll operating current pll at 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) 600 a 9 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter (rms) f vco = 48 mhz f vco = 100 mhz 120 50 ps ps 10 j acc_pll pll accumulated jitter over 1s (rms) f vco = 48 mhz f vco = 100 mhz 1350 600 ps ps 10 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 11 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. the deviation is relative to the factory trimmed frequency at nominal v dd and 25 c, f ints_ft . 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32 = 0. 4. the resulting system clock frequencies must not exceed their maximum specified values. the dco frequency deviation ( 6.3.2.1 oscillator dc electrical specifications table 20. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) 32 khz 4 mhz 8 mhz (range=01) 16 mhz 24 mhz 32 mhz 500 200 300 950 1.2 1.5 na ?a ?a ?a ma ma 1 i ddosc supply current high gain mode (hgo=1) 32 khz 4 mhz 8 mhz (range=01) 16 mhz 24 mhz 32 mhz 25 400 500 2.5 3 4 ?a ?a ?a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m? 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m? feedback resistor high-frequency, low-power mode (hgo=0) m? feedback resistor high-frequency, high-gain mode (hgo=1) 1 m? r s series resistor low-frequency, low-power mode (hgo=0) k? series resistor low-frequency, high-gain mode (hgo=1) 200 k? series resistor high-frequency, low-power mode (hgo=0) k? series resistor high-frequency, high-gain mode (hgo=1) 0 k? table continues on the next page... peripheral operating reuirements and behaviors l2 sub-family data sheet data sheet, rev. 2, 10/201. 2 freescale semiconductor, inc. table 20. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer?s recommendation 3. c x ,c y can be provided by using the integrated capacitors when the low frequency oscillator (range = 00) is used. for all other cases external capacitors must be used. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 oscillator frequency specifications table 21. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high- frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 48 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 27 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 6.4 memories and memory interfaces 6.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 22. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 ?s t hversscr sector erase high-voltage time 13 113 ms 1 t hversall erase all high-voltage time 52 452 ms 1 1. maximum time based on expectations at cycling end-of-life. 6.4.1.2 flash timing specifications commands table 23. flash command timing specifications symbol description min. typ. max. unit notes t rd1sec1k read 1s section execution time (flash sector) 60 ?s 1 t pgmchk program check execution time 45 ?s 1 t rdrsrc read resource execution time 30 ?s 1 t pgm4 program longword execution time 65 145 ?s t ersscr erase flash sector execution time 14 114 ms 2 t rd1all read 1s all blocks execution time 1.8 ms t rdonce read once execution time 25 ?s 1 t pgmonce program once execution time 65 ?s t ersall erase all blocks execution time 88 650 ms 2 t vfykey verify backdoor access key execution time 30 ?s 1 1. assumes 25 mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 28 freescale semiconductor, inc. 6.4.1.3 flash high voltage current behaviors table 24. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 6.4.1.4 reliability specifications table 25. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40 c ? t j ? 125 c. 6.5 security and integrity modules there are no specifications necessary for the device?s security and integrity modules. 6.6 analog 6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 26 and table 27 are achievable on the differential pins adcx_dp0, adcx_dm0. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 29 6.6.1.1 16-bit adc operating conditions table 26. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v r as v as c as z as v adin z adin r adin r adin r adin r adin c adin input pin input pin input pin input pin table continues on the next page... peripheral operating reuirements and behaviors l2 sub-family data sheet data sheet, rev. 2, 10/201. freescale semiconductor, inc. 1 table 27. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 . min. typ. 2 max. unit notes e fs full-scale error 12-bit modes <12-bit modes ?4 ?1.4 ?5.4 ?1.8 lsb 4 v adin = v dda 5 e q quantization error 16-bit modes ?13-bit modes ?1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode avg = 32 avg = 4 16-bit single-ended mode avg = 32 avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit differential mode avg = 32 16-bit single-ended mode avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode avg = 32 16-bit single-ended mode avg = 32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu?s voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 32 freescale semiconductor, inc. 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 8. adc conversion clock < 3 mhz figure 7. typical enob vs. adc_clk for 16-bit differential mode figure 8. typical enob vs. adc_clk for 16-bit single-ended mode peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 33 6.6.2 cmp and 6-bit dac electrical specifications table 28. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 ?a i ddls supply current, low-speed mode (en=1, pmode=0) 20 ?a v ain analog input voltage v ss ? 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 cr0[hystctr] = 00 cr0[hystctr] = 01 cr0[hystctr] = 10 cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd ? 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 ?s i dac6b 6-bit dac current adder (enabled) 7 ?a inl 6-bit dac integral non-linearity ?0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity ?0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd ?0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 34 freescale semiconductor, inc. 0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 9. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 35 0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm p 10 11 vin level (v) figure 10. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 29. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or vrefh. 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 36 freescale semiconductor, inc. 6.6.3.2 12-bit dac operating behaviors table 30. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 250 ?a i dda_dach p supply current high-speed mode 900 ?a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 ?s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 ?s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 ?s 1 v dacoutl dac output voltage range low high-speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr 100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 %fsr 5 e g gain error 0.1 %fsr 5 psrr power supply rejection ratio, v dda ? 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 ?v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance (load = 3 k? ) figure 11. typical inl error vs. digital code peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 38 freescale semiconductor, inc. figure 12. offset at half scale vs. temperature 6.7 timers see general switching specifications . 6.8 communication interfaces 6.8.1 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit usb.org . ereraloeragreuremesabeaors ubamlaaeeaaeee.. reescaleemcoucorc. 6.8.2 usb vreg electrical specifications table 31. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 125 186 ?a i ddstby quiescent current standby mode, load current equal zero 1.1 10 ?a i ddoff quiescent current shutdown mode vregin = 5.0 v and temperature=25 c across operating voltage and temperature 650 4 na ?a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v run mode standby mode 3 2.1 3.3 2.8 3.6 3.6 v v v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.1 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 ?f esr external output capacitor equivalent series resistance 1 100 m? i lim short circuit current 290 ma 1. typical values assume vregin = 5.0 v, temp = 25 c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . 6.8.3 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. see the spi chapter of the chip?s reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. all timing is shown with respect to 20% v dd and 80% v dd thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pf maximum load on all spi pins. table 32. spi master mode timing on slew rate disabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 table continues on the next page... peripheral operating reuirements and behaviors l2 sub-family data sheet data sheet, rev. 2, 10/201. 0 freescale semiconductor, inc. table 32. spi master mode timing on slew rate disabled pads (continued) num. symbol description min. max. unit note 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns 6 t su data setup time (inputs) 18 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 15 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph - 25 ns t fi fall time input 11 t ro rise time output 25 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). for spi1 f periph is the system clock (f sys ). 2. t periph = 1/f periph table 33. spi master mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns 6 t su data setup time (inputs) 96 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 52 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph - 25 ns t fi fall time input 11 t ro rise time output 36 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). for spi1 f periph is the system clock (f sys ). 2. t periph = 1/f periph peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 41 (output) (output) miso (input) mosi (output) ss 1 (output) 2 8 6 7 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 9 5 5 3 (cpol 0) (cpol 1) 4 11 11 10 10 spsck spsck = = 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. figure 13. spi master mode timing (cpha = 0) < table 34. spi slave mode timing on slew rate disabled pads (continued) num. symbol description min. max. unit note 6 t su data setup time (inputs) 2.5 ns 7 t hi data hold time (inputs) 3.5 ns 8 t a slave access time t periph ns 3 9 t dis slave miso disable time t periph ns 4 10 t v data valid (after spsck edge) 31 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t periph - 25 ns t fi fall time input 13 t ro rise time output 25 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). for spi1 f periph is the system clock (f sys ). 2. t periph = 1/f periph 3. time to data active from high-impedance state 4. hold time to high-impedance state table 35. spi slave mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation 0 f periph /4 hz 1 2 t spsck spsck period 4 x t periph ns 2 3 t lead enable lead time 1 t periph 4 t lag enable lag time 1 t periph 5 t wspsck clock (spsck) high or low time t periph - 30 ns 6 t su data setup time (inputs) 2 ns 7 t hi data hold time (inputs) 7 ns 8 t a slave access time t periph ns 3 9 t dis slave miso disable time t periph ns 4 10 t v data valid (after spsck edge) 122 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t periph - 25 ns t fi fall time input 13 t ro rise time output 36 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). for spi1 f periph is the system clock (f sys ). 2. t periph = 1/f periph 3. time to data active from high-impedance state 4. hold time to high-impedance state peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 43 (input) (input) mosi (input) miso (output) ss (input) 2 10 6 7 msb in bit 6 . . . 1 lsb in slave msb slave lsb out bit 6 . . . 1 11 5 5 3 8 (cpol 0) (cpol 1) 4 13 note: not defined 12 12 11 see 13 note 9 see note spsck spsck = = figure 15. spi slave mode timing (cpha = 0) (input) (input) mosi (input) miso (output) 2 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 5 5 10 12 13 11 (cpol 0) (cpol 1) ss (input) 3 12 13 4 note: not defined slave 8 9 see note spsck spsck = = figure 16. spi slave mode timing (cpha = 1) 6.8.4 inter-integrated circuit interface (i 2 c) timing table 36. i 2 c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 khz table continues on the next page... peripheral operating reuirements and behaviors l2 sub-family data sheet data sheet, rev. 2, 10/201. freescale semiconductor, inc. table 36. i 2 c timing (continued) characteristic symbol standard mode fast mode unit minimum maximum minimum maximum hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.3 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd ; dat 0 1 3.45 2 0 3 0.9 1 s data set-up time t su ; dat 250 4 100 2 , 5 ns rise time of sda and scl signals t r 1000 20 +0.1c b 6 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 5 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns 1. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the sda and scl lines. 2. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 3. input signal slew = 10 ns and output load = 50 pf 4. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 5. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat ? 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 6. c b = total capacitance of the one bus line in pf. ? ? 6.8.6 i2s/sai switching specifications this section provides the ac timing for the i2s/sai module in master mode (clocks are driven) and slave mode (clocks are input). all timing is given for noninverted serial clock polarity (tcr2[bcp] is 0, rcr2[bcp] is 0) and a noninverted frame sync (tcr4[fsp] is 0, rcr4[fsp] is 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (bclk) and/or the frame sync (fs) signal shown in the following figures. 6.8.6.1 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 37. i2s/sai master mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk (as an input) pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15.5 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 19 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 26 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 46 freescale semiconductor, inc. s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 18. i2s/sai timing master modes table 38. i2s/sai slave mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 10 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 33 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 10 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 28 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 47 s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 19. i2s/sai timing slave modes 6.8.6.2 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 39. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 48 freescale semiconductor, inc. s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 20. i2s/sai timing master modes table 40. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 49 s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 21. i2s/sai timing slave modes 6.9 human-machine interfaces (hmi) 6.9.1 tsi electrical specifications table 41. tsi electrical specifications symbol description min. typ. max. unit tsi_runf fixed power consumption in run mode 100 a tsi_runv variable power consumption in run mode (depends on oscillator?s current selection) 1.0 128 a tsi_en power consumption in enable mode 100 a tsi_dis power consumption in disable mode 1.2 a tsi_ten tsi analog enable time 66 s tsi_cref tsi reference capacitor 1.0 pf tsi_dvolt voltage variation of vp & vm around nominal values 0.19 1.03 v 7 dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. dimensions kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 50 freescale semiconductor, inc. to find a package drawing, go to freescale.com aerformaeorsearcfore ragsocumeumber fouaeragforsacage eusesocumeumber ou . galullegassgmes efollogablesosesgalsaalableoeacaelocaosofese soeecessuorebsocume.eororoloulesresosble forselecgcfucoalsaalableoeac. ame efaul a a a a b b ou ubamlaaeeaaeee.. reescaleemcoucorc. 64 lqfp 48 qfn 32 qfn pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 18 14 9 pte30 dac0_out/ adc0_se23/ cmp0_in4 dac0_out/ adc0_se23/ cmp0_in4 pte30 tpm0_ch3 tpm_clkin1 19 pte31 disabled pte31 tpm0_ch4 20 15 pte24 disabled pte24 tpm0_ch0 i2c0_scl 21 16 pte25 disabled pte25 tpm0_ch1 i2c0_sda 22 17 10 pta0 swd_clk tsi0_ch1 pta0 tpm0_ch5 swd_clk 23 18 11 pta1 disabled tsi0_ch2 pta1 uart0_rx tpm2_ch0 24 19 12 pta2 disabled tsi0_ch3 pta2 uart0_tx tpm2_ch1 25 20 13 pta3 swd_dio tsi0_ch4 pta3 i2c1_scl tpm0_ch0 swd_dio 26 21 14 pta4 nmi_b tsi0_ch5 pta4 i2c1_sda tpm0_ch1 nmi_b 27 pta5 disabled pta5 usb_clkin tpm0_ch2 i2s0_tx_bclk 28 pta12 disabled pta12 tpm1_ch0 i2s0_txd0 29 pta13 disabled pta13 tpm1_ch1 i2s0_tx_fs 30 22 15 vdd vdd vdd 31 23 16 vss vss vss 32 24 17 pta18 extal0 extal0 pta18 uart1_rx tpm_clkin0 33 25 18 pta19 xtal0 xtal0 pta19 uart1_tx tpm_clkin1 lptmr0_alt1 34 26 19 pta20 reset_b pta20 reset_b 35 27 20 ptb0/ llwu_p5 adc0_se8/ tsi0_ch0 adc0_se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl tpm1_ch0 36 28 21 ptb1 adc0_se9/ tsi0_ch6 adc0_se9/ tsi0_ch6 ptb1 i2c0_sda tpm1_ch1 37 29 ptb2 adc0_se12/ tsi0_ch7 adc0_se12/ tsi0_ch7 ptb2 i2c0_scl tpm2_ch0 38 30 ptb3 adc0_se13/ tsi0_ch8 adc0_se13/ tsi0_ch8 ptb3 i2c0_sda tpm2_ch1 39 31 ptb16 tsi0_ch9 tsi0_ch9 ptb16 spi1_mosi uart0_rx tpm_clkin0 spi1_miso 40 32 ptb17 tsi0_ch10 tsi0_ch10 ptb17 spi1_miso uart0_tx tpm_clkin1 spi1_mosi 41 ptb18 tsi0_ch11 tsi0_ch11 ptb18 tpm2_ch0 i2s0_tx_bclk 42 ptb19 tsi0_ch12 tsi0_ch12 ptb19 tpm2_ch1 i2s0_tx_fs 43 33 ptc0 adc0_se14/ tsi0_ch13 adc0_se14/ tsi0_ch13 ptc0 extrg_in audiousb_ sof_out cmp0_out i2s0_txd0 44 34 22 ptc1/ llwu_p6/ rtc_clkin adc0_se15/ tsi0_ch14 adc0_se15/ tsi0_ch14 ptc1/ llwu_p6/ rtc_clkin i2c1_scl tpm0_ch0 i2s0_txd0 45 35 23 ptc2 adc0_se11/ tsi0_ch15 adc0_se11/ tsi0_ch15 ptc2 i2c1_sda tpm0_ch1 i2s0_tx_fs 46 36 24 ptc3/ llwu_p7 disabled ptc3/ llwu_p7 uart1_rx tpm0_ch2 clkout i2s0_tx_bclk 47 vss vss vss 48 vdd vdd vdd 49 37 25 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx tpm0_ch3 i2s0_mclk pinout kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 52 freescale semiconductor, inc. 64 lqfp 48 qfn 32 qfn pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 50 38 26 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_alt2 i2s0_rxd0 cmp0_out 51 39 27 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_mosi extrg_in i2s0_rx_bclk spi0_miso i2s0_mclk 52 40 28 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_miso audiousb_ sof_out i2s0_rx_fs spi0_mosi 53 ptc8 cmp0_in2 cmp0_in2 ptc8 i2c0_scl tpm0_ch4 i2s0_mclk 54 ptc9 cmp0_in3 cmp0_in3 ptc9 i2c0_sda tpm0_ch5 i2s0_rx_bclk 55 ptc10 disabled ptc10 i2c1_scl i2s0_rx_fs 56 ptc11 disabled ptc11 i2c1_sda i2s0_rxd0 57 41 ptd0 disabled ptd0 spi0_pcs0 tpm0_ch0 58 42 ptd1 adc0_se5b adc0_se5b ptd1 spi0_sck tpm0_ch1 59 43 ptd2 disabled ptd2 spi0_mosi uart2_rx tpm0_ch2 spi0_miso 60 44 ptd3 disabled ptd3 spi0_miso uart2_tx tpm0_ch3 spi0_mosi 61 45 29 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi1_pcs0 uart2_rx tpm0_ch4 62 46 30 ptd5 adc0_se6b adc0_se6b ptd5 spi1_sck uart2_tx tpm0_ch5 63 47 31 ptd6/ llwu_p15 adc0_se7b adc0_se7b ptd6/ llwu_p15 spi1_mosi uart0_rx spi1_miso 64 48 32 ptd7 disabled ptd7 spi1_miso uart0_tx spi1_mosi 8.2 kl26 pinouts the following figures show the pinout diagrams for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see kl26 signal multiplexing and pin assignments . pinout kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 53 pte24 pte31 pte30 pte29 vssa vrefl vrefh vdda pte23 pte22 pte21 pte20 vregin vout33 usb0_dm usb0_dp vss vdd pte1 pte0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2 ptd1 ptd0 ptc11 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6/rtc_clkin ptc0 ptb19 ptb18 ptb17 ptb16 ptb3 ptb2 ptb1 ptb0/llwu_p5 pta20 pta19 pta18 vss vdd pta13 pta12 pta5 pta4 pta3 pta2 pta1 pta0 pte25 figure 22. kl26 64-pin lqfp pinout diagram pinout kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 54 freescale semiconductor, inc. vssa vrefl vrefh vdda pte21 pte20 vregin vout33 usb0_dm usb0_dp vss vdd 12 11 10 9 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2 ptd1 ptd0 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 36 35 34 33 ptc3/llwu_p7 ptc2 ptc1/llwu_p6/rtc_clkin ptc0 32 31 30 29 28 27 26 25 ptb17 ptb16 ptb3 ptb2 ptb1 ptb0/llwu_p5 pta20 pta19 pta3 pta2 pta1 pta0 24 23 22 21 20 19 18 17 pte25 pte24 pte30 pte29 16 15 14 13 pta18 vss vdd pta4 figure 23. kl26 48-pin qfn pinout diagram pinout kl26 sub-family data sheet data sheet, rev. 2, 10/2013. freescale semiconductor, inc. 55 32 31 30 29 28 27 26 25 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 pta2 pta1 pta0 pte30 12 11 10 9 vss vdd pta4 pta3 16 15 14 13 ptb0/llwu_p5 pta20 pta19 pta18 24 23 22 21 20 19 18 17 ptc3/llwu_p7 ptc2 ptc1/llwu_p6/rtc_clkin ptb1 vssa vdda vregin vout33 usb0_dm usb0_dp vss pte0 8 7 6 5 4 3 2 1 figure 24. kl26 32-pin qfn pinout diagram pinout kl26 sub-family data sheet data sheet, rev. 2, 10/2013. 56 freescale semiconductor, inc. document number: kl 2 6 p64m48sf 5 rev . 2 10/2013 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, energy efficient solutions logo, and kinetis are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm and cortex are the registered trademarks of arm limited. ? 2013 freescale semiconductor, inc. |
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